Structure type to access the System Control Block (SCB). More...

#include </home/travis/build/forGGe/theCore/platform/tm4c/export/platform/execution.hpp>

Data Fields
__I uint32_t	CPUID

__IO uint32_t	ICSR

__IO uint32_t	VTOR

__IO uint32_t	AIRCR

__IO uint32_t	SCR

__IO uint32_t	CCR

__IO uint8_t	SHP [12]

__IO uint32_t	SHCSR

__IO uint32_t	CFSR

__IO uint32_t	HFSR

__IO uint32_t	DFSR

__IO uint32_t	MMFAR

__IO uint32_t	BFAR

__IO uint32_t	AFSR

__I uint32_t	PFR [2]

__I uint32_t	DFR

__I uint32_t	ADR

__I uint32_t	MMFR [4]

__I uint32_t	ISAR [5]

uint32_t	RESERVED0 [5]

__IO uint32_t	CPACR

Detailed Description

Structure type to access the System Control Block (SCB).

Field Documentation

◆ CPUID

__I uint32_t SCB_Type::CPUID

Offset: 0x000 (R/ ) CPUID Base Register

◆ ICSR

__IO uint32_t SCB_Type::ICSR

Offset: 0x004 (R/W) Interrupt Control and State Register

◆ VTOR

__IO uint32_t SCB_Type::VTOR

Offset: 0x008 (R/W) Vector Table Offset Register

◆ AIRCR

__IO uint32_t SCB_Type::AIRCR

Offset: 0x00C (R/W) Application Interrupt and Reset Control Register

◆ SCR

__IO uint32_t SCB_Type::SCR

Offset: 0x010 (R/W) System Control Register

◆ CCR

__IO uint32_t SCB_Type::CCR

Offset: 0x014 (R/W) Configuration Control Register

◆ SHP

__IO uint8_t SCB_Type::SHP[12]

Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)

◆ SHCSR

__IO uint32_t SCB_Type::SHCSR

Offset: 0x024 (R/W) System Handler Control and State Register

◆ CFSR

__IO uint32_t SCB_Type::CFSR

Offset: 0x028 (R/W) Configurable Fault Status Register

◆ HFSR

__IO uint32_t SCB_Type::HFSR

Offset: 0x02C (R/W) HardFault Status Register

◆ DFSR

__IO uint32_t SCB_Type::DFSR

Offset: 0x030 (R/W) Debug Fault Status Register

◆ MMFAR

__IO uint32_t SCB_Type::MMFAR

Offset: 0x034 (R/W) MemManage Fault Address Register

◆ BFAR

__IO uint32_t SCB_Type::BFAR

Offset: 0x038 (R/W) BusFault Address Register

◆ AFSR

__IO uint32_t SCB_Type::AFSR

Offset: 0x03C (R/W) Auxiliary Fault Status Register

◆ PFR

__I uint32_t SCB_Type::PFR[2]

Offset: 0x040 (R/ ) Processor Feature Register

◆ DFR

__I uint32_t SCB_Type::DFR

Offset: 0x048 (R/ ) Debug Feature Register

◆ ADR

__I uint32_t SCB_Type::ADR

Offset: 0x04C (R/ ) Auxiliary Feature Register

◆ MMFR

__I uint32_t SCB_Type::MMFR[4]

Offset: 0x050 (R/ ) Memory Model Feature Register

◆ ISAR

__I uint32_t SCB_Type::ISAR[5]

Offset: 0x060 (R/ ) Instruction Set Attributes Register

◆ RESERVED0

uint32_t SCB_Type::RESERVED0[5]

◆ CPACR

__IO uint32_t SCB_Type::CPACR

Offset: 0x088 (R/W) Coprocessor Access Control Register

The documentation for this struct was generated from the following file:

platform/tm4c/export/platform/execution.hpp

Data Fields