theCore C++ embedded framework
platform/tm4c/export/platform/execution.hpp File Reference

Execution control for TM4C platform. More...

#include <stdbool.h>
#include <stdint.h>
#include <sysctl.h>
#include <systick.h>
#include <limits.h>
#include <interrupt.h>
#include <hw_nvic.h>
#include <hw_types.h>
#include <hw_memmap.h>
#include <aux/platform_defines.hpp>
Include dependency graph for platform/tm4c/export/platform/execution.hpp:
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Data Structures

struct  CoreDebug_Type
 Structure type to access the Core Debug Register (CoreDebug). More...
 
struct  DWT_Type
 Structure type to access the Data Watchpoint and Trace Register (DWT). More...
 
struct  SCB_Type
 Structure type to access the System Control Block (SCB). More...
 

Namespaces

 ecl
 

Macros

#define __I   volatile const
 
#define __O   volatile
 
#define __IO   volatile
 
#define __IM   volatile const /*! Defines 'read only' structure member permissions */
 
#define __OM   volatile /*! Defines 'write only' structure member permissions */
 
#define __IOM   volatile /*! Defines 'read / write' structure member permissions */
 
#define SCB_ICSR_VECTACTIVE_Pos   0
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
 
#define CoreDebug_DEMCR_TRCENA_Pos   24U
 
#define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)
 
#define DWT_CTRL_CYCCNTENA_Pos   0U
 
#define DWT_CTRL_CYCCNTENA_Msk   (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
 
#define SCS_BASE   (0xE000E000UL)
 
#define SCB_BASE   (SCS_BASE + 0x0D00UL)
 
#define SCB   ((SCB_Type *) SCB_BASE )
 
#define CoreDebug_BASE   (0xE000EDF0UL)
 
#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE)
 
#define DWT   ((DWT_Type *) DWT_BASE )
 

Functions

 ecl::__attribute__ ((noreturn)) static inline void abort()
 Aborts execution of currently running code. Never return. More...
 
static void ecl::wfi ()
 Waits for interrupts. More...
 
static void ecl::wfe ()
 Waits for events. More...
 
static void ecl::spin_wait (uint32_t ms)
 Performs a dummy busy wait for specified amount of milliseconds. More...
 

Detailed Description

Execution control for TM4C platform.

Macro Definition Documentation

◆ __I

#define __I   volatile const

defines 'read only' permissions

◆ __O

#define __O   volatile

defines 'write only' permissions

◆ __IO

#define __IO   volatile

defines 'read / write' permissions

◆ __IM

#define __IM   volatile const /*! Defines 'read only' structure member permissions */

◆ __OM

#define __OM   volatile /*! Defines 'write only' structure member permissions */

◆ __IOM

#define __IOM   volatile /*! Defines 'read / write' structure member permissions */

◆ SCB_ICSR_VECTACTIVE_Pos

#define SCB_ICSR_VECTACTIVE_Pos   0

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Msk

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)

SCB ICSR: VECTACTIVE Mask

◆ CoreDebug_DEMCR_TRCENA_Pos

#define CoreDebug_DEMCR_TRCENA_Pos   24U

CoreDebug DEMCR: TRCENA Position

◆ CoreDebug_DEMCR_TRCENA_Msk

#define CoreDebug_DEMCR_TRCENA_Msk   (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

◆ DWT_CTRL_CYCCNTENA_Pos

#define DWT_CTRL_CYCCNTENA_Pos   0U

DWT CTRL: CYCCNTENA Position

◆ DWT_CTRL_CYCCNTENA_Msk

#define DWT_CTRL_CYCCNTENA_Msk   (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)

DWT CTRL: CYCCNTENA Mask

◆ SCS_BASE

#define SCS_BASE   (0xE000E000UL)

System Control Space Base Address

◆ SCB_BASE

#define SCB_BASE   (SCS_BASE + 0x0D00UL)

System Control Block Base Address

◆ SCB

#define SCB   ((SCB_Type *) SCB_BASE )

SCB configuration struct

◆ CoreDebug_BASE

#define CoreDebug_BASE   (0xE000EDF0UL)

Core Debug Base Address

◆ CoreDebug

#define CoreDebug   ((CoreDebug_Type *) CoreDebug_BASE)

Core Debug configuration struct

◆ DWT

#define DWT   ((DWT_Type *) DWT_BASE )

DWT configuration struct